CircuitSpace helps designers reduce board layout and placement time from weeks to minutes with AutoClustering technology, intelligent design (IP) reuse and replication.
CircuitSpace implements a hierarchical approach to printed circuit board design through enhanced AutoClustering, design reuse and replication technologies. Using the software designers can create functional groups of components that are intelligently linked between schematic and layout. With the AutoCluster feature designers achieve the same results that, by hand, would typically require tedious, time-consuming and error-prone effort. CircuitSpace extracts data directly from the schematic and automatically gathers components into interconnected groups called clusters in the layout. Once a cluster is created a rough placement of the components is performed, simplifying the task of manual placement and layout.
Designs are revised during the course of a project and from board to board. CircuitSpace propagates changes and helps designers manage them effectively. Checkpoint reports describe a board’s current state, enumerating clusters, members and nets. Designers can save and compare design checkpoints at any time during a design project. Comparison reports identify the difference between a checkpoint report and a board, or another check point report. Designers can review the additions to a cluster’s membership before modifying the actual cluster.
- Create functional groups of components with AutoClustering
- Bi-directional communication between Cadence Allegro and OrCAD PCB Editor and a (PDF) schematic is possible through cross-probing.
- Create multiple replicas of a source cluster’s net topology.
- Propagate cluster membership, placement and shape changes to specified clusters.
- Save a design checkpoint at any time and compare it against other checkpoints.
- Automated change report between layout designs.
- Create a cluster from a specified group of components.
- Propagate cluster reference designator text locations to target clusters.
- Create templates containing a cluster’s membership, net topology, and placement information.
- Template generation for global library usage across divisions.
- Reuse design templates in new or legacy designs.